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dc.contributor.authorAl-Ali, OAK
dc.contributor.authorAnani, Nader
dc.contributor.authorAl-Araji, S
dc.contributor.authorAl-Qutayri, M
dc.date.accessioned2019-11-18T09:23:03Z
dc.date.available2019-11-18T09:23:03Z
dc.date.issued2013-11-26
dc.identifier.citationAl-Kharji Al-Ali, O., Anani, N., Al-Araji, S. and Al-Qutayri, M. (2013) A nonuniform DPLL architecture for optimized performance, IEEJ Transactions on Electrical and Electronic Engineering, 9(1), pp. 15-23.en
dc.identifier.issn1931-4973en
dc.identifier.doi10.1002/tee.21931en
dc.identifier.urihttp://hdl.handle.net/2436/622927
dc.description.abstractThis paper presents the design, analysis, simulation, and implementation of the architecture of a new nonuniform-type digital phase-locked loop (DPLL). The proposed loop uses a composite phase detector (CPD), which consists of a sample-and-hold unit and an arctan block. The CPD improves the system linearity and results in a wider lock range. In addition, the loop has an adaptive controller block, which can be used to minimize the overall system sensitivity to variations in the power of the input signal. Furthermore, the controller has a tuning mechanism that gives the designer the flexibility to customize the loop parameters to suit a particular application. These performance parameters include lock range, acquisition time, phase noise or jitter, and signal-to-noise ratio enhancement. The simulation results show that the proposed loop provides flexibility to optimize the major conflicting system parameters. A prototype of the proposed system was implemented using a field-programmable gate array (FPGA), and the practical results concur with those obtained by simulation using MATLAB/Simulink. © 2013 Institute of Electrical Engineers of Japan.en
dc.formatapplication/pdfen
dc.languageen
dc.language.isoenen
dc.publisherWileyen
dc.relation.urlhttps://onlinelibrary.wiley.com/doi/full/10.1002/tee.21931en
dc.subjectacquisition timeen
dc.subjectcomposite phase detectoren
dc.subjectdigital phase-locked loopen
dc.subjectjitteren
dc.subjectlock rangeen
dc.subjectnoiseen
dc.titleA nonuniform DPLL architecture for optimized performanceen
dc.typeJournal articleen
dc.identifier.eissn1931-4981
dc.identifier.journalIEEJ Transactions on Electrical and Electronic Engineeringen
dc.date.updated2019-11-11T17:02:23Z
dc.date.accepted2012-09-22
rioxxterms.funderJiscen
rioxxterms.identifier.projectUOW18112019NAen
rioxxterms.versionAMen
rioxxterms.licenseref.urihttps://creativecommons.org/licenses/by-nc/4.0/en
rioxxterms.licenseref.startdate2019-11-18en
dc.source.volume9
dc.source.issue1
dc.source.beginpage15
dc.source.endpage23
dc.description.versionPublished version
refterms.dateFCD2019-11-18T09:22:23Z
refterms.versionFCDAM
refterms.dateFOA2019-11-18T09:23:04Z


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