Abstract
This paper presents the design, analysis, simulation, and implementation of the architecture of a new nonuniform-type digital phase-locked loop (DPLL). The proposed loop uses a composite phase detector (CPD), which consists of a sample-and-hold unit and an arctan block. The CPD improves the system linearity and results in a wider lock range. In addition, the loop has an adaptive controller block, which can be used to minimize the overall system sensitivity to variations in the power of the input signal. Furthermore, the controller has a tuning mechanism that gives the designer the flexibility to customize the loop parameters to suit a particular application. These performance parameters include lock range, acquisition time, phase noise or jitter, and signal-to-noise ratio enhancement. The simulation results show that the proposed loop provides flexibility to optimize the major conflicting system parameters. A prototype of the proposed system was implemented using a field-programmable gate array (FPGA), and the practical results concur with those obtained by simulation using MATLAB/Simulink. © 2013 Institute of Electrical Engineers of Japan.Citation
Al-Kharji Al-Ali, O., Anani, N., Al-Araji, S. and Al-Qutayri, M. (2013) A nonuniform DPLL architecture for optimized performance, IEEJ Transactions on Electrical and Electronic Engineering, 9(1), pp. 15-23.Publisher
WileyJournal
IEEJ Transactions on Electrical and Electronic EngineeringAdditional Links
https://onlinelibrary.wiley.com/doi/full/10.1002/tee.21931Type
Journal articleLanguage
enISSN
1931-4973EISSN
1931-4981ae974a485f413a2113503eed53cd6c53
10.1002/tee.21931
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Except where otherwise noted, this item's license is described as https://creativecommons.org/licenses/by-nc/4.0/