Show simple item record

dc.contributor.authorHahne, Christopher
dc.contributor.authorLumsdaine, Andrew
dc.contributor.authorAggoun, Amar
dc.contributor.authorVelisavljevic, Vladan
dc.date.accessioned2018-05-22T14:18:01Z
dc.date.available2018-05-22T14:18:01Z
dc.date.issued2018-03-22
dc.identifier.citationReal-Time Refocusing using an FPGA-based Standard Plenoptic Camera 2018:1 IEEE Transactions on Industrial Electronics
dc.identifier.issn0278-0046
dc.identifier.doi10.1109/TIE.2018.2818644
dc.identifier.urihttp://hdl.handle.net/2436/621296
dc.description.abstractPlenoptic cameras are receiving increasing attention in scientific and commercial applications because they capture the entire structure of light in a scene, enabling optical transforms (such as focusing) to be applied computationally after the fact, rather than once and for all at the time a picture is taken. In many settings, real-time interactive performance is also desired, which in turn requires significant computational power due to the large amount of data required to represent a plenoptic image. Although GPUs have been shown to provide acceptable performance for real-time plenoptic rendering, their cost and power requirements make them prohibitive for embedded uses (such as in-camera). On the other hand, the computation to accomplish plenoptic rendering is well-structured, suggesting the use of specialized hardware. Accordingly, this paper presents an array of switch-driven Finite Impulse Response (FIR) filters, implemented with FPGA to accomplish high-throughput spatial-domain rendering. The proposed architecture provides a power-efficient rendering hardware design suitable for full-video applications as required in broadcasting or cinematography. A benchmark assessment of the proposed hardware implementation shows that real-time performance can readily be achieved, with one order of magnitude performance improvement over a GPU implementation and three orders of magnitude performance improvement over a general-purpose CPU implementation.
dc.formatapplication/PDF
dc.language.isoen
dc.publisherIEEE
dc.relation.urlhttp://ieeexplore.ieee.org/document/8322307/
dc.subjectComputer vision
dc.subject3D imaging
dc.subjectFPGA
dc.titleReal-Time Refocusing using an FPGA-based Standard Plenoptic Camera
dc.typeJournal article
dc.identifier.eissn1557-9948
dc.identifier.journalIEEE Transactions on Industrial Electronics
dc.date.accepted2018-03-02
rioxxterms.funderUniversity of Wolverhampton
rioxxterms.identifier.projectUOW22052018AA
rioxxterms.versionAM
rioxxterms.licenseref.urihttps://creativecommons.org/licenses/by-nc-nd/4.0/
rioxxterms.licenseref.startdate2020-11-11
dc.source.volume65
dc.source.issue12
dc.source.beginpage9757
dc.source.endpage9766
refterms.dateFCD2018-10-19T09:24:44Z
refterms.versionFCDAM
refterms.dateFOA2018-08-21T15:26:54Z
html.description.abstractPlenoptic cameras are receiving increasing attention in scientific and commercial applications because they capture the entire structure of light in a scene, enabling optical transforms (such as focusing) to be applied computationally after the fact, rather than once and for all at the time a picture is taken. In many settings, real-time interactive performance is also desired, which in turn requires significant computational power due to the large amount of data required to represent a plenoptic image. Although GPUs have been shown to provide acceptable performance for real-time plenoptic rendering, their cost and power requirements make them prohibitive for embedded uses (such as in-camera). On the other hand, the computation to accomplish plenoptic rendering is well-structured, suggesting the use of specialized hardware. Accordingly, this paper presents an array of switch-driven Finite Impulse Response (FIR) filters, implemented with FPGA to accomplish high-throughput spatial-domain rendering. The proposed architecture provides a power-efficient rendering hardware design suitable for full-video applications as required in broadcasting or cinematography. A benchmark assessment of the proposed hardware implementation shows that real-time performance can readily be achieved, with one order of magnitude performance improvement over a GPU implementation and three orders of magnitude performance improvement over a general-purpose CPU implementation.


Files in this item

Thumbnail
Name:
TIE2818644 (2).pdf
Size:
3.855Mb
Format:
PDF

This item appears in the following Collection(s)

Show simple item record